switchboard.sbdut module
Note that the sbdut module inherits functions from siliconcompiler.Chips, such as input() used to add rtl files to the simulation and add() used to add include directories to the simulation. These functions are important for specifying the RTL files used in a simulation, but they are not covered in the documentation here. For a complete list of the the inherited functions, checkout the siliconcompiler documentation.
Class inheriting from the SiliconCompiler Chip class that can be used for building a Switchboard-based testbench.
This class is meant to be interacted with like a regular Chip object, but it has some parameters automatically configured to abstract away setup of files that are required by all Switchboard testbenches.
Classes:
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Functions:
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- class switchboard.sbdut.SbDut(design='testbench', tool='verilator', default_main=True, trace=True, trace_type='vcd', module=None, fpga=False, xyce=False, frequency=100000000.0, period=None, max_rate=-1, start_delay=None, timeunit=None, timeprecision=None, warnings=None, cmdline=False, fast=False, extra_args=None, autowrap=False, parameters=None, interfaces=None, clocks=None, resets=None, tieoffs=None, buildroot=None, builddir=None, args=None, subcomponent=False, suffix=None, threads=None)[source]
Bases:
Chip- Parameters:
design (string) – Name of the top level chip design module.
tool (string, optional) – Which tool to use to compile simulator. Options are “verilator” or “icarus”.
default_main (bool, optional) – If True, the default testbench.cc will be used and does not need to be provided via the add() function
trace (bool, optional) – If true, a waveform dump file will be produced using the file type specified by trace_type.
trace_type (str, optional) – File type for the waveform dump file. Defaults to vcd.
module (str, optional) – module containing the siliconcompiler driver for this object
fpga (bool, optional) – If True, compile using switchboard’s library of modules for FPGA emulation, rather than the modules for RTL simulation.
xyce (bool, optional) – If True, compile for xyce co-simulation.
frequency (float, optional) – If provided, the default frequency of the clock generated in the testbench, in seconds.
period (float, optional) – If provided, the default period of the clock generated in the testbench, in seconds.
max_rate (float, optional) – If provided, the maximum real-world rate that the simulation is allowed to run at, in Hz. Can be useful to encourage time-sharing between many processes and for performance modeling when latencies are large and/or variable.
start_delay (float, optional) – If provided, the real-world time to delay before the first clock tick in the simulation. Can be useful to make sure that programs start at approximately the same time and to prevent simulations from stepping on each other’s toes when starting up.
warnings (List[str], optional) – If provided, a list of tool-specific warnings to enable. If not provided, a default set of warnings will be included. Warnings can be disabled by setting this argument to an empty list.
cmdline (bool, optional) – If True, accept configuration settings from the command line, such as “–trace”, “–tool TOOL”, and “–fast”.
fast (bool, optional) – If True, the simulation binary will not be rebuilt if an existing one is found. The setting here can be overridden when build() is called by setting its argument with the same name.
extra_args (dict, optional) – If provided and cmdline=True, a dictionary of additional command line arguments to be made available. The keys of the dictionary are the arguments (“-n”, “–test”, etc.) and the values are themselves dictionaries that contain keyword arguments accepted by argparse (“action”: “store_true”, “default”: 42, etc.)
timeunit (str)
timeprecision (str)
autowrap (bool)
- build(cwd=None, fast=None)[source]
- Parameters:
cwd (str, optional) – Working directory for the simulation build
fast (bool, optional) – If True, the simulation binary will not be rebuilt if an existing one is found. Defaults to the value provided to the SbDut constructor, which in turn defaults to False.
- input_analog(filename, pins=None, name=None, check_name=True, dir=None)[source]
Specifies a SPICE subcircuit to be used in a mixed-signal simulation. This involves providing the path to the SPICE file containing the subcircuit definition and describing how real-valued outputs in the SPICE subcircuit should be converted to binary values in the Verilog simulation (and vice versa for subcircuit inputs).
Each of these conversions is specified as an entry in the “pins” argument, which is a list of dictionaries, each representing a single pin of the SPICE subcircuit. Each dictionary may have the following keys: * “name”: name of the pin. Bus notation may be used, e.g. “myBus[7:0]”. In that case, it is expected that the SPICE subcircuit has pins corresponding to each bit in the bus, e.g. “myBus[0]”, “myBus[1]”, etc. * “type”: direction of the pin. May be “input”, “output”, or “constant”. If “constant”, then this pin will not show up the Verilog module definition to be instantiated in user code. Instead, the SPICE subcircuit pin with that name will be tied off to a fixed voltage specified in the “value” field (below). * “vil”: low voltage threshold, below which a real-number voltage from the SPICE simulation is considered to be a logical “0”. * “vih”: high voltage threshold, above which a real-number voltage from the SPICE simulation is considered to be a logical “1”. * “vol”: real-number voltage to pass to a SPICE subcircuit input when the digital value driven is “0”. * “voh”: real-number voltage to pass to a SPICE subcircuit input when the digital value driven is “1”. * “tr”: time taken in the SPICE simulation to transition from a logic “0” value to a logic “1” value. * “tf”: time taken in the SPICE simulation to transition from a logic “1” value to a logic “0” value. * “initial”: initial value of a SPICE subcircuit pin. Currently only implemented for subcircuit outputs. This is sometimes helpful, because there is a slight delay between t=0 and the time when the SPICE simulation reports values for its outputs. Specifying “initial” for subcircuit outputs prevents the corresponding digital signals from being driven to “X” at t=0.
- Parameters:
filename (str) – The path of the SPICE file containing the subcircuit definition.
pins (List[Dict[str, Any]]) – List of dictionaries, each describing a pin of the subcircuit.
name (str) – Name of the SPICE subcircuit that will be instantiated in the mixed-signal simulation. If not provided, Switchboard guesses that the name is filename stem. For example, if filename=”myCircuit.cir”, then Switchboard will guess that the subcircuit name is “myCircuit”
check_name (bool) – If True (default), Switchboard parses the provided file to make sure that there is a subcircuit definition matching the given name.
dir (str) – Running a mixed-signal simulation involves creating SPICE and Verilog wrappers. This argument specifies the directory where those wrappers should be written. If not provided, defaults to the directory where filename is located.
- simulate(plusargs=None, args=None, extra_args=None, cwd=None, trace=None, period=None, frequency=None, max_rate=None, start_delay=None, run=None, intf_objs=True)[source]
- Parameters:
plusargs (str or list or tuple, optional) – additional arguments to pass to simulator that must be preceded with a +. These are listed after args.
args (str or list or tuple, optional) – additional arguments to pass to simulator listed before plusargs and extra_args
extra_args (str or list or tuple, optional) – additional arguments to pass to simulator listed after args and plusargs
cwd (str, optional) – working directory where simulation binary is saved
trace (bool, optional) – If true, a waveform dump file will be produced
period (float, optional) – If provided, the period of the clock generated in the testbench, in seconds.
frequency (float)
max_rate (float)
start_delay (float)
run (str)
intf_objs (bool)
- Return type:
Popen